Alif Semiconductor /AE302F80F55D5AE_CM55_HP_View /CGU /ESCLK_SEL

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Interpret as ESCLK_SEL

ES1_OSC=Val_0x0, ES1_PLL=Val_0x0, ES0_PLL=Val_0x0, ES0_OSC=Val_0x0

Description

Clock Select Register for M55-HP and M55-HE

Fields

ES0_PLL	Select PLL clock frequency for RTSS_HP_CLK 0 (Val_0x0): Select 100 MHz PLL clock 1 (Val_0x1): Select 200 MHz PLL clock 2 (Val_0x2): Select 300 MHz PLL clock 3 (Val_0x3): Select 400 MHz PLL clock
ES1_PLL	Select PLL clock frequency for RTSS_HE_CLK 0 (Val_0x0): Select 60 MHz PLL clock 1 (Val_0x1): Select 80 MHz PLL clock 2 (Val_0x2): Select 120 MHz PLL clock 3 (Val_0x3): Select 160 MHz PLL clock
ES0_OSC	Select oscillator clock frequency for RTSS_HP_CLK 0 (Val_0x0): Select 76.8 MHz ring-oscillator clock 1 (Val_0x1): Select 38.4 MHz ring-oscillator clock 2 (Val_0x2): Select 76.8 MHz crystal-oscillator clock 3 (Val_0x3): Select 38.4 MHz crystal-oscillator clock
ES1_OSC	Select oscillator clock frequency for RTSS_HE_CLK 0 (Val_0x0): Select 76.8 MHz ring-oscillator clock 1 (Val_0x1): Select 38.4 MHz ring-oscillator clock 2 (Val_0x2): Select 76.8 MHz crystal-oscillator clock 3 (Val_0x3): Select 38.4 MHz crystal-oscillator clock

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